1. Field of the Invention
The present invention relates generally to waveform synthesizers and, more particularly, to their use as pin drivers in interface circuits of automatic test equipment.
2. Description of the Related Art
An exemplary use of transistor waveform synthesizers can be found in the field of automatic test equipment (ATE) where test waveforms are generated and applied to leads of devices under test (DUTs). Because these waveforms are typically applied via an ATE "pin" (i.e., a terminal), circuits configured for this purpose are typically referred to as "pin drivers". Preferably, the magnitudes, common-mode components and timing of pin-driver waveforms can be individually adjusted to accommodate a variety of DUTs and, in addition, the waveforms should have fast, symmetric rising and falling edges with minimal transients (i.e., spurious signals). Because ATEs typically employ a large number (e.g., 1024) of pin drivers, costs are significantly reduced if they are realized with simple circuits.
A first exemplary pin driver is shown in U.S. Pat. No. 4,572,971 to couple a level selector circuit to a DUT with a buffer circuit. The level selector circuit is arranged to accommodate reference voltages that represent both small and large voltage swings. In response to first and second reference voltages and a current switch, the level selector circuit generates a signal equal to a selected one of the reference voltages at an output node. The output node signals are applied to the DUT through a unity-gain buffer circuit having two stages that each comprise a complementary emitter follower.
A second exemplary pin driver is disclosed in U.S. Pat. No. 5,842,155 which couples a pulse forming circuit to a DUT with buffer and amplifier stages. The pulse forming network responds to high and low signal inputs by respectively charging and discharging a network node with currents of equal magnitudes so as to achieve pulses having equal positive and negative slew rates between pulse magnitudes equal to the high and low inputs. The pulses thus formed at the network node are then applied to the DUT through unity-gain buffer and amplifier stages which each comprise a complementary emitter follower structure.
Although these exemplary pin drivers can generate pulse signals with controlled amplitudes, they fail to provide for independent adjustment of a common-mode component and are relatively complex (e.g., the pulse forming circuit and buffer and amplifier stages of U.S. Pat. No. 5,842,155 include 11 transistors and the components of U.S. Pat. No. 4,572,971 are even more numerous.
Another exemplary pin driver has been formed with a buffer amplifier, a differential pair and a resistor. The resistor couples a DUT to the output of the buffer amplifier and the DUT is also coupled to the collector of one of the differential pair's transistors. A common-mode signal can then be applied to the input of the buffer amplifier and a data signal (e.g., a digital signal) applied to a differential input of the differential pair. In response to the data signal, the differential pair steers the current of a programmable current source to flow through the resistor and change the data voltage applied to the DUT. The common-mode signal applied to the DUT is thus controlled via the buffer amplifier and the amplitude of the data signal is varied via the programmed current of the current source.
Although this latter pin driver circuit facilitates the automatic control required in ATEs and is much simpler and accordingly less expensive than the first and second exemplary pin drivers, its generated waveforms generally include undesired spurious signals. For example, FIG. 1 illustrates a typical waveform 10 from this pin driver. It includes a falling edge 11 that descends a lower waveform level 12 and a rising edge 13 that ascends to an upper waveform level 14. Although the edges are steep and substantially linear, there is typically a pronounced overshoot 15 as the falling edge transitions to the lower level 12.
Because the performance of modern electronic circuits is constantly increasing, there is a demand for simple, inexpensive circuits that can generate high-speed test waveforms whose fidelity is superior to that of the waveform 10. In addition to applying test waveforms to DUTs, modern ATEs are also generally required to verify that the DUT can sink or source specified currents and to verify that the DUT provides specified response waveforms. To provide these functions at each DUT lead, a respective ATE interface circuit preferably contains a waveform synthesizer, an active load and a comparator.